Lam Research Corporation
Information Technology · Semiconductors & Semiconductor Equipment
Memory-cycle exposure with leading-edge logic optionality:
- Memory exposure (NAND staircase etch, DRAM capacitor etch, HBM TSV) is the largest single growth surface - the 2024-2026 memory cycle (driven by HBM + AI training data) is Lam-friendly.
- Leading-edge logic GAA transistor formation needs Lam's atomic-layer etch + atomic-layer deposition (ALE / ALD); wallet share rises with each node transition.
- High-aspect-ratio etch for 3D NAND scaling (1Tb → 2Tb → 4Tb per die) keeps the NAND-side cycle alive even when bit shipments are flat - each layer of NAND scaling is an etch + deposition tool sale.
Bear:
- Heavy NAND exposure - when NAND undersupply ends, Lam's order book softens fastest.
- Same TSMC + Samsung + Micron + SK Hynix concentration as $AMAT.
- China-trailing-edge has been a partial offset; tighter export controls erode that hedge.
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